Integration Verification Across Software and Hardware for a Simple Embedded System
The interfaces between layers of a system are susceptible to bugs if developers of adjacent layers proceed under subtly different assumptions. Formal verification of two layers against the same formal model of the interface between them can be used to shake out these bugs. Doing so for every interface in the system can, in principle, yield unparalleled assurance of the correctness and security of the system as a whole. However, there have been remarkably few efforts that carry out this exercise, and all of them have simplified the task by restricting interactivity of the application, inventing new simplified instruction sets, and using unrealistic input and output mechanisms. We report on the first verification of a realistic embedded system, with its application software, device drivers, compiler, and RISC-V processor represented inside the Coq proof assistant as one mathematical object, with a machine-checked proof of functional correctness. A key challenge is structuring the proof modularly, so that further refinement of the components or expansion of the system can proceed without revisiting the rest of the system.
Thu 21 OctDisplayed time zone: Central Time (US & Canada) change
15:40 - 17:00 | |||
15:40 15mTalk | Automatically Enforcing Fresh and Consistent Inputs in Intermittent Systems SIGPLAN Papers Milijana Surbatovich Carnegie Mellon University, Limin Jia Carnegie Mellon University, Brandon Lucia Carnegie Mellon University, USA | ||
15:55 15mTalk | IOOpt- Automatic Derivation of I/O complexity bounds for affine programs SIGPLAN Papers Auguste Olivry Inria, France, Guillaume Iooss Inria, Nicolas Tollenaere Inria, Atanas Rountev Ohio State University, Saday Sadayappan University of Utah, USA, Fabrice Rastello Inria, France | ||
16:10 15mTalk | Integration Verification Across Software and Hardware for a Simple Embedded System SIGPLAN Papers Andres Erbsen MIT, Samuel Gruetter Massachusetts Institute of Technology, Joonwon Choi Massachusetts Institute of Technology, USA, Clark Wood Massachusetts Institute of Technology, Adam Chlipala Massachusetts Institute of Technology | ||
16:25 15mTalk | Execution reconstruction: Harnessing failure reoccurrences for failure reproduction SIGPLAN Papers Gefei Zuo University of Michigan, Jiacheng Ma University of Michigan, Andrew Quinn University of Michigan, Pramod Bhatotia University of Edinburgh, Pedro Fonseca Purdue University, Baris Kasikci University of Michigan, USA | ||
16:40 20mLive Q&A | Discussion, Questions and Answers SIGPLAN Papers |