Registered user since Wed 12 Jun 2019
My research focuses on formalising the process of converting high-level programming language descriptions to correct hardware that is functionally equivalent to the input. This process is called high-level synthesis (HLS), and allows software to be turned into custom accelerators automatically, which can then be placed on field-programmable gate arrays (FPGAs). An implementation in the Coq theorem prover called Vericert can be found on Github.
|SPLASH 2021|| Formal Verification of High-Level Synthesis|
Formal Verification of High-Level Synthesis
|Show activities from other conferences|